1. Field of the Invention
The present invention concerns integrated circuit (IC) design, and particularly relates to techniques for placement and routing of circuits during IC design.
2. Description of the Related Art
FIG. 1 provides a representational illustration of a typical integrated circuit (IC) chip (or die) 10 which includes a semiconductor substrate 12, upon which are formed the electronic devices used to implement the chip""s functionality. The logic circuitry of the integrated circuit is formed on the interior portion 20 of the semiconductor substrate 12. The logic portion 20 includes a number of functional circuit blocks that can have different sizes and shapes. The larger blocks can include, for example, central processing units such as CPU 21, read-only memories such as ROM 22, clock/timing units such as clock/timing unit 23, random access memories such as RAMs 24, input/output (I/O) units such as I/O unit 25 for providing an interface between CPU 21 and peripheral devices, and phase-locked loops (PLLs) such as PLL 26. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries. The logic portion further includes tens of thousands, hundreds of thousands or even millions of additional small cells 27. Each cell 27 represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries. As used herein, the term xe2x80x9ccellsxe2x80x9d refers generically to macroblocks, such as elements 21 to 26, as well as small cells 27.
Along the periphery of the semiconductor substrate are I/O buffer cells 16. More specifically, each of the I/O buffer cells 16 is either a power signal buffer, a ground buffer or an information signal buffer. As used herein, the term xe2x80x9cinformation signalxe2x80x9d is defined to mean a signal that conveys any type of information and includes, for example, clock, data, address and control signals. In a wire-bond IC chip, each such buffer cell 16 generally has connected to it at least one metal bonding pad 18 which is used as an electrical connection for an I/O signal.
The wire-bond IC die is mounted within a plastic or ceramic package having multiple pins, and wire connections are made between the die""s bonding pads and the package""s pins. Finally, the package containing the IC die is mounted onto a printed circuit board in a manner so as to form electrical connections between the pins of the IC and other components on the printed circuit board. In this manner, external signals can be provided to and from the IC die.
Certain of pads 18 are connected to external power (VDD) and ground (VSS). Each such pad is connected to a buffer cell, which in turn is connected to one of the chip""s power or ground rings, as the case may be. More specifically, power ring 32 and ground ring 33 supply power and ground to the buffer cells 16. Similarly, power ring 30 and ground ring 31 provide power and ground to the internal logic circuitry 20. In order to isolate the internal logic power and ground from the l/O buffer power and ground, ordinarily certain pad/buffer pairs are connected only to the internal logic power/ground rings 32 and 33, and different pad/buffer pairs are connected only to the buffer power/ground rings. To further isolate the power/ground supplies for certain sensitive circuits from the power/ground supplies for noisier circuits, cuts are made in the rings (not shown). Each resulting ring segment can then be used to supply a different type of circuit. Moreover, although only a single I/O power ring 32 is shown, mixed-voltage integrated circuits may utilize a different power ring for each different voltage.
In integrated circuit design, the physical design is the process of generating, from a circuit description, a design which can be directly fabricated on an IC die. Physical design ordinarily begins with a list of devices (or nets) and interconnections between the nets, called a xe2x80x9cnetlistxe2x80x9d. Initially, the physical design phase ordinarily obtains, from a cell library, descriptions for a number of cells corresponding to the nets specified in the netlist. Different cells therefore exist for information signal buffers, power/ground buffers and the various internal logic circuits. Each cell is pre-defined and contains physical design information to implement its circuitry. As a result, physical design need not focus on the transistor-level, but can be accomplished by first laying out the obtained cells across the surface of the semiconductor substrate and then routing connections between the cells.
In more detail, the layout phase of physical design is the process of determining exact physical locations and orientations for each cell. The routing phase of physical design is the process of describing actual physical electrical trace connections between the laid-out cells based on the interconnections specified in the netlist. Completion of layout and routing must result in a physical design that is feasible, in the sense that the design can be implemented physically. Thus, for example, routing must be accomplished in the available space and without undesired wire crossings. In addition, layout and routing ideally should result in a physical design which is as compact as possible, in order to reduce fabrication costs, as well as to minimize the effects of long signal travel times.
However, a typical integrated circuit often will contain tens of thousands, hundreds of thousands or even millions of cells. Accordingly, to accomplish layout and routing relatively quickly and efficiently, computer-aided design (CAD) tools are used extensively. Even with such tools, the physical design problem is believed to be NP-complete, meaning that an exact solution ordinarily can not be obtained in polynomial time. CAD tools therefore typically rely on heuristic rules to obtain a good solution in a reasonable amount of time. Moreover, in order to insure that such CAD tools can be used in a wide variety of circumstances, it is usually desirable to make these heuristics as generally applicable as possible.
Unfortunately, certain circuits included in an IC are especially sensitive to noise. Therefore, it is often desirable to impose additional specific layout and routing rules with respect to each such circuit. However, conforming to these special-case rules often can be difficult when using a more or less general-purpose CAD tool, and modifying the CAD tool to accommodate each such case is often impractical. As a result, when such noise-sensitive circuits are to be implemented in an integrated circuit, significant user input frequently is required.
One example of a noise-sensitive circuit for which additional layout and routing rules are often required is a phase-locked loop (PLL). In one representative case, it has been determined that the following layout and routing rules should be satisfied to effectively isolate a given PLL from noise:
the PLL should have access to dedicated I/O buffers, power/ground ring cuts and dummy cells arranged as shown in FIG. 2
the most sensitive PLL signal, LP2, should be routed using multi-grid width wire, and the trace for LP2 should be surrounded on each side by traces for PLLVSS
no other wire should be closer than a predetermined fixed distance to the PLLVSS wires surrounding LP2
all PLL power and ground signals should have widths equal to the corresponding PLL terminal widths
PLLAGND should be shorted to PLLVSS at a location as close to the PLL as possible
a fixed isolation area should be maintained around the PLL, i.e., no other cells or wires should be placed within the isolation area
As noted above, FIG. 2 illustrates the dedicated power, ground and information signal I/O buffers, as well as the power/ground ring arrangement, for the PLL. In FIG. 2, cuts 45 form a PLL VSS segment 47 and a PLL VDD segment 48 from VSS ring 49 and VDD ring 50, respectively. Accordingly, segments 47 and 48 can be used to supply power and ground exclusively to the PLL and its buffers, thereby reducing noise effects from other circuits. Element 51 is the bonding pad for inputting PLLVSS, which is the externally supplied ground signal for the PLL. Bonding pad 52 is for inputting PLLLP2, which is the externally supplied LP2 control signal that controls the voltage-controlled oscillator portion of the PLL. Bonding pad 53 is for inputting PLLAGND, which is the ground signal for an external RC filter. Bonding pad 54 is for inputting PLLVDD, which is the externally supplied power. Bonding pad 55 is for inputting the clock signal CLK. Bonding pads 51 to 55 are implemented on the semiconductor substrate of the IC die, and are electrically connected to corresponding I/O buffers 61 to 65, respectively, also implemented on the semiconductor substrate. The output of buffer 61 (PLLVSS) and the output of buffer 64 (PLLVDD) are connected to PLL VSS segment 47 and PLL VDD segment 48, respectively. The outputs of buffers 62 (PLLLP2), 63 (PLLAGND) and 65 (CLK) are routed to the PLL during the routing phase of physical design, in accordance with the above-specified rules. Finally, as shown in FIG. 2, attached to the PLL segments of the power/ground rings are dummy cells 58 which are padless devices provided for electrostatic discharge (ESD) protection.
Thus, in conventional layout and routing, the user typically is required to remember each of the above special-case rules and to insure that each is implemented. For instance, many CAD layout tools will only route in single-grid width wire. Accordingly, PLLLP2 generally must be routed manually. Similarly, the user must verify that each of the other rules has been satisfied, or else must make appropriate adjustments. This task is complicated by the fact that each different noise-sensitive circuit will ordinarily have its own particular set of special layout and routing rules. As a result, layout and routing of noise-sensitive circuits can be difficult and time-consuming. Moreover, if the user forgets or fails to implement even one of these rules, performance of the IC can be impaired. In addition, subsequent troubleshooting to determine the cause of the impaired performance may prove difficult.
The present invention addresses the foregoing problems by providing a single cell which includes a signal processing portion, a buffer portion and an interconnection between the two.
According to one aspect, the invention is directed to a cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
According to a further aspect, the invention is directed to a cell for inclusion in a cell library used in designing integrated circuits. The cell includes a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included, as well as a noise-sensitive signal processing circuit which performs signal processing unrelated to buffering performed by said buffer circuit. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
According to a still further aspect, the invention is directed to a cell library for use in designing integrated circuits, the library including a cell which includes (1) a signal processing circuit; (2) a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included; and (3) layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
According to a still further aspect, the invention is directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells. According to this aspect of the invention, one of the cells obtained from the cell library, referred to as a combined cell, includes (1) a signal processing circuit; (2) a buffer circuit for buffering a signal external to the integrated circuit in which the combined cell is to be included; and (3) layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit.
By virtue of the foregoing arrangements, the present invention often can simplify layout and routing for certain signal processing circuits, particularly circuits requiring special layout and/or routing rules. Moreover, the foregoing arrangements often can reduce the chance of user error in neglecting to satisfy any one of such rules.